In general, a semiconductor integrated circuit needs a relatively long time period from a power switch on-event to a ready for operation state due to unstable power voltage level. This is because of the fact that power consuming circuits of the integrated circuit have not yet initialized yet, so that some power consuming circuits are put into oscillation states and another power consuming circuit such as an inverter circuit is switched into simultaneous on-states of the component transistors coupled in series between a source of voltage and a ground terminal. These unstable power consuming circuits consume a large amount of electric power which can exceed the capability of the power supply circuit incorporated in the integrated circuit, and, for this reason, the integrated circuit needs a relatively long time period to become ready for the operational state.
For acceleration to the stable state, a semiconductor integrated circuit employs a prohibition circuit, and a typical example of the prohibition circuit is illustrated in FIG. 1 of the drawings. The prohibition circuit illustrated in FIG. 1 comprises a first series combination of p-channel MOS type field effect transistors 1 and 2 and an n-channel MOS type field effect transistor 3 coupled between a source of power voltage Vdd and a ground terminal, a second series combination of a p-channel MOS type field effect transistor 4 and an n-channel MOS type field effect transistor 5, and two inverter circuits 6 and 7 coupled in series. The second series combination serves as an inverter circuit which is similar in circuit arrangement of each of the inverter circuit 6 and 7. The p-channel MOS type field effect transistor 1 has a gate electrode coupled to a first node N1 provided between the two p-channel MOS type field effect transistors 1 and 2 and the n-channel MOS type field effect transistor 2 has a gate electrode coupled to a second node N2 provided between the two MOS type field effect transistors 2 and 3 different in channel conductivity type from each other, but the n-channel MOS type field effect transistor 3 has a gate electrode coupled to the source of power voltage Vdd. The second node N2 in turn is coupled to gate electrodes of the two MOS type field effect transistor forming the second series combination, and the second series combination has a third node N3 provided between the two component MOS type field effect transistors 4 and 5. The third node N3 is coupled to the input node of the inverter circuit 6 and the two inverter circuits 6 and 7 respectively have fourth and fifth nodes N4 and N5 serving as the respective output nodes. As to current driving capabilities of the MOS type field effect transistors, the n-channel MOS type field effect transistor 3 is very much smaller in current driving capability than each of the p-channel MOS type field effect transistors 1 and 2, but the p-channel MOS type field effect transistor 4 is very much smaller in current driving capability than the n-channel MOS type field effect transistor 5.
The prior-art prohibition circuit thus arranged is operative to produce a control signal S1 supplied to a switching transistor forming part of the power consuming circuit ( not shown ) which has a probability of the oscillation or the simultaneous on-states of the component transistors. Assuming now that all of the p-channel MOS type field effect transistors 1, 2 and 4 and all of the n-channel MOS type field effect transistors 3 and 5 have respective threshold voltages Vtp and Vtn which are identical in absolute value V.sub.THab with each other.
Prior to the power switch on-operation, all of the nodes N1 to N5 are in the ground voltage level as will be seen from FIG. 2 of the drawings When the power switch is shifted from the off-state to the on-state, the voltage level VL supplied from the source of power voltage Vdd is gradually increased, but the p-channel MOS type field effect transistor 1 does not turn on until the voltage level VL reaches a voltage level approximately equal to the absolute value V.sub.THab. However, if the voltage level VL exceeds the absolute value V.sub.THab at time t1, the p-channel MOS type field effect transistor 1 turns on to provide a conduction path between the source of power voltage Vdd and the first node N1, then the first node N1 begins to go up in parallel to the voltage level VL. Similarly, the p-channel MOS type field effect transistor 2 does not turn on until a voltage level V.sub.N1 at the first node N1 reaches a voltage level approximately equal to the absolute value V.sub.THab, so that a voltage level V.sub.N2 at the second node N2 remains in the ground level in this stage.
If the voltage level VL exceed a voltage level twice as large as the absolute value V.sub.THab at time t2, the voltage level V.sub.N1 also exceeds the voltage level approximately equal to the absolute value V.sub.THab, thereby allowing the p-channel MOS type field effect transistor 2 to turn on. Although the n-channel type MOS field effect transistor 3 is turned on, the n-channel MOS type field effect transistor 3 is very much smaller in current driving capability than the p-channel MOS type field effect transistor 2. This means that the voltage level V.sub.N2 is increased in substantially parallel to the voltage level V.sub.N1 and, accordingly, to the voltage level VL. However, voltage level V.sub.N3 at the third node N3 remains in the ground level until the voltage level V.sub.N2 reaches the voltage level approximately equal to the absolute value V.sub.THab. Then, the p-channel MOS type field effect transistor 4 is turned off to keep a voltage level V.sub.N3 at the third node N3 in the ground level until time t1; however the voltage level V.sub.N3 at the third node N3 is increased in parallel to the voltage level V.sub.N1 after time t1 because the n-channel MOS type field effect transistor 5 is turned off. Each of the inverter circuits 6 and 7 is similar in circuit arrangement as described hereinbefore, so that a voltage level V.sub.N5 at the fifth node N5 or the control signal S1 is also increased identically with the voltage level V.sub.L. The switching transistor of the power consuming circuit is designed to be turned off in the voltage level V.sub.N5 over the absolute value V.sub.THab . The power consuming circuit is protected from the oscillation or the simultaneous on-states of the component transistors. If the voltage level VL reaches a voltage level approximately three times larger than the absolute value V.sub.THab at time t3, the voltage level V.sub.N2 also reaches the voltage level approximately equal to the absolute value V.sub.THab, so that the n-channel MOS type field effect transistor 5 turns on to provide a conduction path between the node N3 and the ground terminal. The voltage level V.sub.N3 rapidly goes down toward the ground voltage level due to the difference in current driving capability between the MOS type field effect transistors 4 and 5, and, accordingly, a voltage level V.sub.N4 at the fourth node N4 goes up over the voltage level approximately twice larger than the absolute value .sub.THab. The result is that the fifth node N5 or the control signal S1 is rapidly decreased in voltage level as shown in FIG. 2, so that the switching transistor turns on to activate the power consuming circuit.
After activation of the power consuming circuit, the voltage level VL is continuously increased to a voltage level approximately five times larger than the absolute value V.sub.THab where no undesirable oscillation or no simultaneous on-states of the component transistors takes place.
However, a problem is encountered in the integrated circuit with the prior-art prohibition circuit illustrated in FIG. 1 in that undesirable circuit operations take place in the power consuming circuits. Specifically, if the prior-art prohibition circuit is incorporated in, for example, a data processing unit, the prohibition circuit prohibits the power consuming circuits of the data processing unit from activation until the stable power voltage level which is three times larger than the absolute value in the example illustrated in FIG. 1. However, the data processing unit is usually supplied with a clock signal from an external clock generator even if the source of power voltage does not reach the stable level. Then, the power consuming circuits begin to carry out the respective operations prior to execution of an initialization program. For example, a power consuming circuit serving as an arithmetic circuit may execute the operation to produce data bits which may be transferred to the outside thereof by another power consuming circuit serving as a data output buffer circuit. The power consuming circuits consume a large amount of electric power during such undesirable operations, so that the power consumption may hardly be reduced in some applications such as a data processing unit.